Modern integrated circuits are formed on the surfaces of semiconductor substrates, which are mostly silicon substrates. Semiconductor devices are isolated from each other by isolation structures formed on the surface of the respective semiconductor substrates. The isolation structures include field oxides and shallow trench isolation (STI) regions.
Field oxides are often formed using local oxidation of silicon (LOCOS). A typical formation process includes blanket forming a mask layer on a silicon substrate, and then patterning the mask layer to expose certain areas of the underlying silicon substrate. A thermal oxidation is then performed in an oxygen-containing environment to oxidize the exposed portions of the silicon substrate. The mask layer is then removed.
With the down-scaling of integrated circuits, STI regions are increasingly used as the isolation structures. Conventionally, STI regions are often formed using one of the two methods, high-density plasma chemical vapor deposition (HDP) and high aspect-ratio process (HARP) for the gap-filling. The HDP may be used to fill gaps with aspect ratios less than about 6.0 without causing voids. The HARP may be used to fill gaps with aspect ratios less than about 7.0 without causing voids.
FIGS. 1 and 2 illustrate intermediate stages in the formation of an STI region. First, an STI opening is formed in substrate 10, for example, by etching. The STI opening has an aspect ratio, which equals to the ratio of depth D1 to width W1. The aspect ratio becomes increasingly greater when the integrated circuits are increasingly scaled down. For 40 nm technology and below, the aspect ratio will be greater, and sometimes far greater, than 7.0. Oxide 12, preferably a silicon oxide, is filled into the opening, until the top surface of oxide 12 is higher than the top surface of silicon substrate 10.
The increase in the aspect ratio causes problems. Referring to FIG. 1, in the filling of the STI opening, the high aspect ratio will adversely result in the formation of void 14, which is a result of the pre-mature sealing in the top region of oxide 12. After a chemical mechanical polish (CMP) to remove excess oxide 12, STI region 16 is left in the opening, as is shown in FIG. 2. It is likely that void 14 is exposed after the CMP. In subsequent process steps, conductive materials such as polysilicon may be filled into the opening, causing the bridging, and even the shorting of integrated circuits in some circumstances.
When the aspect ratios are high, even if no voids are formed, the central portions (seam) of STI regions formed using HARP are often weak. This is typically caused by the inactivity of C2H5 terminals in the STI regions. Since the oxides formed by HARP are highly conformal, the sidewall portions eventually join each other, forming seams such as seam 15 in FIGS. 1 and 2. With the inactive C2H5 terminals, even if the sidewall portions are in physical contact, there are few bonds formed. As a result, the seams are mechanically weak. The seams may be damaged by the CMP processes, which may in turn cause voids after the CMP. When the aspect ratios further increase to greater than 7.0, voids start to appear even if the HARP is used. Accordingly, the existing gap-filling techniques can only fill gaps having aspect ratios less than 7.0 without causing voids or weak seams.
U.S. Pat. No. 7,033,945 teaches a method including the steps of forming a STI opening, partially filling the STI opening with BSG, performing a reflow to re-shape the BSG, performing a dip in HF acid, and then performing a second filling step to fully fill the STI opening. However, such process incurs extra cost of reflowing the BSG, and may also reduce the throughput. New gap-filling methods are thus needed.